MODULE bg
TITLE 'Blanking Generator'
"
" E-mail: chan@elm-chan.org
" Homepage: http://elm-chan.org/
"
" This will able to be fitted to most CPLD. Following pin numbers are
" for Lattice ispLSI1016E-80LJ used as U7 in "YCbCr to RGB converter".

" Inputs
CLK4        pin 11;                 " Master clock (14.3MHz)
!CSIN       pin 8;                  " Composite sync input


" Outputs
CLK         pin 43 istype 'reg';    " 3.58MHz for NTSC encoder
!BLANK      pin 5  istype 'com';    " Blanking
!CLAMP      pin 3  istype 'reg';    " DC clamp
!CSOUT      pin 41 istype 'com';    " Bufferred composite sync
!HDOUT      pin 16 istype 'com';    " Half-H killed horizontal sync
!PON        pin 38 istype 'com';    " Power control


" Nodes
Hblank             node istype 'reg';  " Blanking indicator
Vblank             node istype 'reg_g';

Hsd1, Hsd2         node istype 'reg';  " Sync edge detector
Vsd1, Vsd2         node istype 'reg_g';
Hc880              node istype 'com';
HsGate,CsGate      node istype 'reg';

CLK2               node istype 'reg';   " 4fsc divider
CLKDIV = [CLK,CLK2];

HC0..HC9           node istype 'reg';   " Horizontal timing counter
HC = [HC9..HC0];

VC0..VC8           node istype 'reg_g'; " Line counter
VC = [VC8..VC0];



" Constants and Symbols

   hsfall =  Hsd1 & !Hsd2;
   hsrise = !Hsd1 &  Hsd2;
   vsfall =  Vsd1 & !Vsd2;

   nLines = 263;    " 263 for NTSC, 313 for PAL
   nVBS = nLines-3; " Vertical blanking start (lines)
   nVBE = 21;       " Vertical blanking end (lines)
   nHBS = 892;      " Horizontal blanking start (CLK4s)
   nHBE = 128;      " Horizontal blanking end (CLK4s)



EQUATIONS

   [CLKDIV, HC, VC, Hsd1, Hsd2, Hblank ,Vsd1, Vsd2, Vblank, CLAMP, CsGate, HsGate].clk = CLK4;
   [VC, Vblank].ce = hsfall & Hc880;
   [Vsd1, Vsd2].ce = (HC == 100);

   " 3.58MHz output
   CLKDIV := CLKDIV + 1;

   " Sync edge detectors
   [Hsd1, Hsd2] := [CSIN, Hsd1];
   [Vsd1, Vsd2] := [CSIN, Vsd1];

   " Horizontal timing counter
        when hsfall & Hc880 then HC := 0;
   else when (HC < 1023)    then HC := HC + 1;
   else                          HC := HC;

   Hc880 = (HC >= 880);
   PON   = (HC < 1023);


   " Vertical timing counter
   when      vsfall         then VC := 5;
   else when (VC == nLines) then VC := 1; 
   else                          VC := VC + 1;

   " Horizontal drive (half-H killed)
   HsGate := CSIN & HsGate
           # Hc880;
   HDOUT = CSIN & HsGate;

   " Horizontal blanking
   when      (HC == nHBS-1) then Hblank := 1;
   else when (HC == nHBE-1) then Hblank := 0;
   else                          Hblank := Hblank;

   " Vertical blanking
   when      (VC == nVBS-1) then Vblank := 1;
   else when (VC == nVBE)   then Vblank := 0;
   else                          Vblank := Vblank;

   " Blanking output (composite)
   BLANK = Hblank # Vblank;

   " DC clamp
   when           (HC >= 120) then CLAMP := 0;
   else when hsrise & !Vblank then CLAMP := 1;
   else                            CLAMP := CLAMP;

   " Bufferred composite sync
   CsGate := CSIN & CsGate
           # Hc880
           # (VC < 10);
   CSOUT = CSIN & CsGate;


END