;----------------------------------------------------------------------------;
; Rainbow illumination driver for three color LED
;

.include "tn12def.inc"	; This file is contained in "AVR Family Assembler".


.def	_Lv0	= r23		;PB0 level (0..64)
.def	_Lv1	= r24		;PB1 level (0..64)
.def	_Lv2	= r25		;PB2 level (0..64)
.def	_Pulse	= r29		;PB3/PB4 flash counter

.def	_Pwm	= r26		;Saw wave generator for PWM
.def	_Tmp	= r27		;Working register for interruput process
.def	_Tmr	= r28		;293Hz decrement timer
.def	_Sreg	= r14		;SREG save register


;----------------------------------------------------------;
; Program code

.cseg
	; Interrupt Vectors
	rjmp	reset		; Reset
	rjmp	0		; INT0
	rjmp	0		; PCINT
;	rjmp	tc0_ov		; OVF0
;	rjmp	0		; EEPROM
;	rjmp	0		; ANA_COMP


tc0_ov:				; TC0.ov interrupt (18.8kHz)
	in	_Sreg, SREG	;Save SREG
	ldi	_Tmp, -1	;Reload timer value
	out	TCNT0, _Tmp	;/

	cpi	_Pulse, -16	;Drive 2 LEDs in alternate flash
	rol	_Tmp		;
	subi	_Pulse, -128	;
	cpi	_Pulse, -16	;
	rol	_Tmp		;
	subi	_Pulse, -128	;/
	cp	_Lv2, _Pwm	;Drive 3 LEDs in PWM
	rol	_Tmp		;
	cp	_Lv1, _Pwm	;
	rol	_Tmp		;
	cp	_Lv0, _Pwm	;
	rol	_Tmp		;/
	out	PORTB, _Tmp	;Output LED driver

	dec	_Pwm		;Update saw wave generator
	brne	PC+4		; and drive 293Hz counter
	ldi	_Pwm, 64	;
	dec	_Tmr		;
	dec	_Pulse		;/

	out	SREG, _Sreg	;Restore SREG
	reti


;----------------------------------------------------------;

reset:
	ldi	ZL, low(FLASHEND*2+1)	;OSCCAL (Stored at end of flash)
	ldi	ZH, high(FLASHEND*2+1)	;
	lpm				;
	out	OSCCAL, r0		;/

	ldi	r16, 0b00011111		;Initialize port B
	out	PORTB, r16		;
	out	DDRB, r16		;/

	ldi	r16, 0b011		;TC0.ck = 1.2M/64 = 18.8k
	out	TCCR0, r16		;/
	ldi	r16, (1<<TOIE0)		;Enable TC0.ov
	out	TIMSK, r16		;/

	ldi	_Lv0, 64		;Initial values for each channel
	ldi	_Lv1, 0			;
	ldi	_Lv2, 0			;/

	sei

ph0:	rcall	delay		;Phase 0: PB2 up ramp
	inc	_Lv2		;
	cpi	_Lv2, 64	;
	brne	ph0		;/
ph1:	rcall	delay		;Phase 1: PB0 down ramp
	dec	_Lv0		;
	brne	ph1		;/
ph2:	rcall	delay		;Phase 2: PB1 up ramp
	inc	_Lv1		;
	cpi	_Lv1, 64	;
	brne	ph2		;/
ph3:	rcall	delay		;Phase 3: PB2 down ramp
	dec	_Lv2		;
	brne	ph3		;/
ph4:	rcall	delay		;Phase 4: PB0 up ramp
	inc	_Lv0		;
	cpi	_Lv0, 64	;
	brne	ph4		;/
ph5:	rcall	delay		;Phase 5: PB1 down ramp
	dec	_Lv1		;
	brne	ph5		;/
	rjmp	ph0		;Continue...


delay:	ldi	_Tmr, 7		;Delay 7 PWM cycles = 24ms
	cpi	_Tmr, 0		;
	brne	PC-1		;/
	ret