General purpose display controller

Hardware

Several years ago, I built a display controller which is same with discrete parts. However, the old CRTC (HD46505 or equivalents) used to the display controller has been discontinued, so that it cannot be obtained.

Recently, some CPLD family, such as Xilinx, Altera and Lattice, are polular in Japanese electronics enthusiasts, so that I also tried to use a Xilinx XC9500 family to learn it and to reduce wiring cost.

Features

At the first time, it determined specifications in consideration of the generality.

The host interface is compatible with SRAM to be connected to most microcontroler directly. It might be connected to the memory socket on the board. For microcontroller which doesn't export the data bus, it can also control it with I/O ports.

Video output format is RGB with composite sync. It will be directly connected to junk CRT/LCD monitors. However, the junk RGB monitor is not that easy to obtain, so it have to be also connected to a TV.

The resolution of 320 by 240 dots is sufficient for video monitors smaller than several ins and TV because their resolution is low. When higher resolution is used, video data should be processed will be much (i.e., it requires faster processor and more memory space). Similarly, number of colors is 16 because it is not for natural picture.

As above trems, the specifications for this display controller is determined as follows:

• Composed with: Only ordinaly parts because this is for experimental use.
• Host interface: SRAM compatible interface to connect most microcontroller easily.
• Screen mode: Full graphic display without character generator to increase display flexibility.
• Resolution: 320 by 240, 4bit/pixel.
• Video outputs: RGB with composite sync, S-Video and C-Video (Encoding for last two is NTSC).

Block Diagram

Right image shows the block diagram for the display controller. The CPLD used for main controller is XC95108(PLCC). It has 108 macrocells and 69 I/O port(some have gloval function), so that it is just suitable for this project.

Most function is integrated into the XC95108, therefore, number of parts and wires could be reduced. The CRTC block is counter array to generate display timing. The timing controller block is the main logic to arbitrate between host access and display access to the video buffer.

Semiconductor parts except CPLD are only an SRAM and a clock oscllator. For video buffer, an 1M bit SRAM is used. In this project, NTSC output is also required except for RGB output, so that a video encoder is added.

Circuit Diagram

This is the circuit diagram for display controller. It is very simple, isn't it? It is using only three ICs, number of wires is reduced compared from previous project. Each part in this project is not special, so that whole parts will be found in Akihabara Electric Town.

As for this degree, It is possible that anyone will build it easily Ofcourse, an envilonment to develop CPLD/FPGA projects is also required :-)

Video data from the XC95108 is converted into RGB signal with a resister matrix. The RGB signal is encoded into NTSC signal by CXA1645, at the same time, it is distributed into RGB, S and Composited video. 3.58MHz color sub-carrier clock to video encoding is generated with CPLD.

Building PCB

Assemble

There is nothing to pay attention to build it. However, basic technic, such as to make firm power line, put bypass capacitors properly, are needed at least. If built it without careful, because of the display controller have digital/analog circuits on the same board, the picture quality will be worse.

The built display controller is shown in right image. In this project, I designed the PCB to distribute it at "Comic Market" in Tokyo. It was very easy to route print pattern because the CPLD can configure its pin out to fit to parts layout. Most pattern is routed on only parts side, most of solder side is occupied by ground plane.

Function Check

The display controller doesn't require any adjustment. It will work completely at the first time if there is not mistake. Please check if there is not wireing miss, and then supply +5V, program fuse data (crtif2a.jed) into XC95108, it will begin to work immediataly. Top image shows an RGB monitor that displays the picture generated by the display controller.

To use a display controller, host controller to control it must be prepared, so that the display controller cannot checked completely without host controller. However, some function except host interface can be checked with it alone. Attach an video monitor and tie VEN# to gorund, at the time, it is ok if random pattern is displayed and synchronized. What pattern is displayed is depend on each SRAM chip.

PLD files and PCB files

How To Use

Pin functions for host interface

XA[15:0] XD[7:0]	Address input and data input/output equivalent to SRAM's address/data.
CE# WR# RD#	Read/write command input equivalent to SRAM's control input. When write a data, set address/data to be written and assert CE# and WR#, the data will be written. When read a data, set address to be read and assert CE# and RD#, the read data will be output to the data bus.
WAIT#	Wait request to the host to expand read/write cycle. It responds and asserted to valid read/write command, and then deasserted at read/write command is completed.
VEN#	VEN# controls video output. When VEN# is asserted, video output is enabled. When VEN# is deasserted, video output is blanked.
DISP	Vertical display indicater (i.e. it is deasserted(low) during vertical blanking). It can be used for interrupt source to perform synchronized drawing.
GND VCC	Power supply. VCC requires +5V DC and 250mA at least.

Interface Timing

Display buffer is read/written by the host controller via the host interface. Because the interfacing protocol is compatible to SRAM, it can be controlled with same method of SRAM access. However, for arbitration between host access and display access, expanding the read/write cycle with WAIT# may be needed by the access timing.

Follows are timing diagrams and timing values for the host interface. The timing diagrams are illustrated as RD#/WR# storobed operation, however, it can also be used in CE# strobed operation.

Item	Description	Min	Max	Unit
tWR	WAIT# response time	-	15	ns
tSU1	Read address setup time (v.s. command input)	0	-	ns
tREAD	Read command execution time	140	485	ns
tH1	Address/command hold time (for read cycle)	0	-	ns
tSU3	Write address/data setup time (v.s. command input)	0	-	ns
tWRITE	Write command execution time	70	415	ns
tSU2	Read data setup time (v.s. rise edge of WAIT#)	15	-	ns
tH2	Address/command/data hold time (for write cycle)	0	-	ns
tON	Bus driver enable time	-	9.5	ns
tOFF	Bus driver disable time	-	9.5	ns
tREC	Access recoverly time	70	-	ns

Memory Map

Hereis the video memory mapping. It becomes resolution of 320 dots horizontal and 240 lines vertical. Each two pixels are packed into one memory location (byte), so that the line size is 160 bytes par line. For example, when a value 24h is written into location 0000h, a red dot appears at top-left and a green dot appears at next to the red dot.

Memory addres range is 64K bytes, display area is from 0000h to 95FFh, invisible area can be used for any other purpose. The display area is shifted to 4000h when AOFS jumper is shorted.

At 240 line mode, upper end and lower end of the picture may be cut out from TV screen. To prevent it, the vertical size can be changed to 200 lines. At the 200 line mode, display memory area is less than 32K bytes, so that it will easy to map to small memory space.

Video Output

Video output format is non-intreraced which is same as TV game. Details for the output format is as follows:

RGB-Video	RGB: 0.7Vp-p (Zo=75ohm) Sync: Horizontal/Vertical composited TTL level, Negative
S-Video	Y: 1.0Vp-p (Zo=75ohm) C: 286mVp-p (Zo=75ohm)
C-Video	1.0Vp-p (Zo=75ohm)

Item	Description	Value	Unit
nHt	Horizontal total time	227.5	ACLK
nHd	Horizontal display time	160	ACLK
nHsp	Horizonta sync position	181	ACLK
nHsw	Horizonta sync width	17	ACLK
nVt	Vertical total time	263	Line
nVd	Vertical display time	240	LIne
nVsp	Vertical sync position	224	Line
nVsw	Vertical sync width	3	Line
-	Horizontal sync frequency	15.73	kHz
-	Vertical sync frequency	59.8	Hz

Internal Timing

Read/write cycle from host controller is inserted into each display cycle. The transfer rate of host access becomes 3.58 Mbytes per second by ACLK is 3.58 MHz

To keep spectrum inter-leave of the color sub-carrier, a half clock delay is added into end of horizontal cycle to adjust horizontal time to 227.5 ACLKs. This is for only NTSC configuration.

Timing chart for internal operation

Half clock delay operation

Changes For Various Use

If you wish to change a part of specs to fit to your use, it may able to be changed in small modification.

8bit I/O Interface

When you wish to attach the display controller to a tiny microcontroller which doesn't have extrenal memory space, it occupies 28 bits of I/O port (16 address, 8 data and four controls). In this case, host intreface can be optimized for 8 bit I/O operation, it occupies only 11 bits of I/O port minimum (8 address/data, 3 controls).

Host interface for 8bit I/O configuration

Control timing for 8bit I/O configuration

PAL video output

This is changes for PAL configuration. Change R10 to 16k ohms, tie pin# 7 to ground, change color sub-carrier clock to external 4.43MHz, and master clock have to be changed to 13.5MHz.

Monochrome VGA

Most Asian character sets require higher resolution at least 640 by 480. In this case, it can be changed to monochrome VGA configuration with some modification. It will also suitable for POS terminal, industrial machine and others. The video memory mapping is same as VGA adapter's mode 11h, so that most graphic library will be used without changes. Right image shows the prototype board which is modified to monochrome VGA configuration.

Output buffer for VGA configuration