This project is an experiment of the Digital Signal Processing with a cheap microcontroller instead of an ordinary digital signal processor. Recent 8 bit microcontrollers have sufficient processing performance so that they can be used for simple audio signal processing.
There are some simple audio processing, such as Delay, Echo, Pitch Conversion, that easy to experiment. In old days, solid state audio processors had realized those audio effects with analog delay elements called BBD(charge coupled device). Mainly this project follows these process in digital signal processing.
Figure 1 shows the block diagram for this project. The microcontroller samples input signal and applies any process, and then output the processed wave form. When the microcontroller has any analog I/O units, such as ADC, DAC and PWM, no additional component is required. However signal processing requires a number of working memory proportional to the data latency so that built-in RAM will not suffice for the process and most case requires any external RAM.
This is the Circuit Diagram for this project. An ATtiny26 which has analog I/O units, is used for digital signal processing. Recently, it have been appeared on the market with very low price. It has 11 10bit-ADC channels and two 8bit-PWM channels for analog interfacing. Since the built-in RAM is only 128 bytes, any external RAM is required. However ATtiny26 has only 16 I/O pins, any port extension may be needed.
I found out a 1Mbit (256Kx4) DRAM in my junk box and tried to use it as an external RAM. It could be attached to the AVR via only 13 I/O ports without any I/O extension. Because multi-bit dynamic RAM has an OE signal and bidirectional data ports, the data ports can share address bus for data transfer after row/column addresses are latched. Thus number of I/O ports could be reduced by the triple multiplexed control. Note that this control method is effective for only FPM/EDO DRAM. The control timings are shown in Figure 2. The byte of a sample data is divided in two nibbles and they are read/written to RAM in page mode cycles. Since the DRAM requires refresh cycles to maintain contents of memory cells, at least minimum required refresh cycles must be inserted into processing loop, e.g. for 32k processing loop per second, 2 refresh cycles are needed every loop. For more details, please refer to the source files.
The A-D converter of ATtiny26 can operate at 15ksps with maximum accuracy or at 77ksps with maximum speed. In this project, 8 bit/38.5 ksps is used mainly so that audio bandwidth of an FM radio will be expected. At 16 MHz operation, 416 clock of processing time is given for each sample.
The ATtiny26 doesn't have D-A converter, however, it has 64 MHz PLL clock for TC1 so that 8 bit/250 kHz PWM output can be used. When use this for analog output, higher cut-off low pass filter can be used and it can cover audio bandwidth.
Value of setup volume is read at first and is used for effect value or any setup data.
Delay line is one of the fundamental processes in digital signal processing. It delays input signal N sample time. This is mostly incorporated into more complicated process as a processing element rather than stand alone use.
Firmware for this process is VP_DLY.ASM. Delay time can be set between 0 and 1.7 seconds with the setting volume.
This is a simple application of Delay. The delayed signal is fed-back to input. Input signal will repeat with reducing its amplitude. The feed-back gain a must be set to less than 1 for proper operation, or the processing loop will oscillate. When feed-forward the delayed data to output with a=1, it will become a comb filter.
Firmware for this process is VP_ECHO.ASM. Echo delay time can be set between 0 and 420 milliseconds with the setting volume. Feed-back gain is fixed to 0.5.
The delay element is realized by an N sample ring buffer (FIFO). What will occur the effect when read rate varies and write rate is left fixed? Of course the pitch of output sound will be changed. This is the pitch conversion process without tempo change called "Pitch Changer".
In actual implement, the processing loop is driven in sampling rate of input signal and output sampling rate is changed equivalency by adjusting increase rate of the read pointer. The fraction of read pointer is used for interpolation to reduce beat distortion. At pitch up process, as a result, it becomes down sampling and aliasing distortion will appear, however, it seems hardly conscious of the distortion.
Since the ring buffer has limited length, pointer cross over will occur in a cycle. At the instant of pointer passing, a wave form for one buffer length is inserted or removed. The wave division granularity affects listenability, too long buffer will drop or double a part of pronunciation, so that a proper buffer length should be chosen with care. According to some trial, around 20 millisecond seems suitable for speech. This requires the buffer length of several hundred samples. Some microcontroller will able to work without external RAM.
Figure 6 shows a movement of read pointer and data flow from the view point of write pointer. When read pointer passes write pointer, the wave form will lose its continuity and it appear as click noise. To suppress this effect, cross fade at block change is applied. In the concrete, pushed out data is stored into blending buffer, the buffer covers opposite end of ring buffer. The cross fade is done during passing this range for 32 sample time.
Firmware for this process is VP_PITCH.ASM. Conversion ratio can be set between 0.5 and 2.0 with the setting volume. Number of multiplication per sample is two or six times for interpolation and boundary blending. This is too heavy process for ATtiny26 which has no multiplier, data losing are occured at 38.5 ksps, so that 32 ksps is used for only this configuration.
This is a variation of pitch conversion. An audio effect like wow/flutter can be generated by modulating read sampling rate. The pointer cross over will not occur with sufficient buffer length and delaying read pointer. Firmware for this process is VP_WOW.ASM.
This is just like digital signal processing in these examples. For the fundamentals of digital filter, please refer to any textbooks on digital signal processing. Figure 8 shows the signal flow diagram of FIR filter. The filter response is determined by filter parameter witch is summing gain for each taps. Larger number of taps increase frequency resolution, however, number of multiply/accumulate operation will also increase proportional to the number of taps.
Since the ATtiny26 does not have multiplier, an unsigned multiply takes 34 clocks. Plus memory access, sign conversion and accumulation are required for each taps, so that number of taps will be very limited. I tried to replace the multiplication with table conversion, it could be take 14 clocks for each taps, 23 taps are secured at 38.5k sps. I have not heard about digital signal processor with no multiplier, however, such the cheap microcontroller seems able to be used as a digital signal processor. The ATmega series microcontroller which has signed unsigned multiplication will take 8 clocks for each taps.
Firmware for this process is VP_FIL.ASM, and multiplication table VP_FIL_M.HEX.
Balanced Modulation is a kind of Amplitude Modulation (AM). Ordinary amplitude modulation uses only positive region of the carrier amplitude (fc * (1 + fs)), and the balanced modulation uses positive and negative region of the carrier amplitude in center value of zero carrier (fc * fs). The balanced modulation is one of the very important process for digital communication technology. When multiply input signal by a carrier signal, many frequency components will be generated due to following formula of sine wave multiplication.
The generated signal is like a "robot voice". Firmware for this process is VP_MOD.ASM. Modulating frequency can be set between 0 Hz and 1200 Hz with the setting volume. added at Apr.13 2004