MODULE lcam_tg TITLE 'Line Camera CCD Driver - Top Level' " Input Pins (LC4256V-75T100C) !CLK pin 89; " Master clock READ pin 5; " FIFO read signal !DREN pin 4; " FIFO data ready enable D0..D7 pin 94..92,86..84,81,80; " FIFO data input (8bit) " Output Pins (LC4256V-75T100C) Q0..Q15 pin 31,30,21..19,17..14,11..8,6,28,29 istype 'com'; " FIFO data output (16bit) !DRDY pin 100 istype 'reg'; " FIFO full signal !SH, CCD pin 99,98 istype 'reg'; " CCD drive clock !SYNC pin 3 istype 'com'; " CCD end of line interrupt " Nodes pc0, pc2..pc11 node istype 'reg'; " Dot counter frp2..frp1 node istype 'reg'; " FIFO R/W pointer den node istype 'reg'; " CCD data enable fd0..fd127 node istype 'reg'; " FIFO registers (16 bytes) wpclr node istype 'reg'; " FIFO rp reset " Symbols and Macros pc = [pc11..pc2, CCD, pc0]; fd = [fd127..fd0]; fd0w = [fd15..fd0]; fd0h = [fd15..fd8]; fd0l = [fd7..fd0]; fd1w = [fd31..fd16]; fd1h = [fd31..fd24]; fd1l = [fd23..fd16]; fd2w = [fd47..fd32]; fd2h = [fd47..fd40]; fd2l = [fd39..fd32]; fd3w = [fd63..fd48]; fd3h = [fd63..fd56]; fd3l = [fd55..fd48]; fd4w = [fd79..fd64]; fd4h = [fd79..fd72]; fd4l = [fd71..fd64]; fd5w = [fd95..fd80]; fd5h = [fd95..fd88]; fd5l = [fd87..fd80]; fd6w = [fd111..fd96]; fd6h = [fd111..fd104]; fd6l = [fd103..fd96]; fd7w = [fd127..fd112]; fd7h = [fd127..fd120]; fd7l = [fd119..fd112]; frp = [frp2..frp1, READ]; frph = [frp2..frp1]; D = [D7..D0]; Q = [Q15..Q0]; EQUATIONS " Counter/TG part [pc, den, SH, wpclr].clk = CLK; when (pc == 2187) then pc := 0; else pc := pc + 1; " Dot counter SH := (pc == 2187) # (pc == 0); " CCD-SH signal SYNC = SH; when (pc == 130) then den := 1; else when (pc == 2178) then den := 0; else den := den; " Data enable wpclr := (pc == 128); " FIFO input part fd.clk = CLK; when (pc & ^b11111 == ^b00100) then fd0l := D; else fd0l := fd0l; when (pc & ^b11111 == ^b00110) then fd0h := D; else fd0h := fd0h; when (pc & ^b11111 == ^b01000) then fd1l := D; else fd1l := fd1l; when (pc & ^b11111 == ^b01010) then fd1h := D; else fd1h := fd1h; when (pc & ^b11111 == ^b01100) then fd2l := D; else fd2l := fd2l; when (pc & ^b11111 == ^b01110) then fd2h := D; else fd2h := fd2h; when (pc & ^b11111 == ^b10000) then fd3l := D; else fd3l := fd3l; when (pc & ^b11111 == ^b10010) then fd3h := D; else fd3h := fd3h; when (pc & ^b11111 == ^b10100) then fd4l := D; else fd4l := fd4l; when (pc & ^b11111 == ^b10110) then fd4h := D; else fd4h := fd4h; when (pc & ^b11111 == ^b11000) then fd5l := D; else fd5l := fd5l; when (pc & ^b11111 == ^b11010) then fd5h := D; else fd5h := fd5h; when (pc & ^b11111 == ^b11100) then fd6l := D; else fd6l := fd6l; when (pc & ^b11111 == ^b11110) then fd6h := D; else fd6h := fd6h; when (pc & ^b11111 == ^b00000) then fd7l := D; else fd7l := fd7l; when (pc & ^b11111 == ^b00010) then fd7h := D; else fd7h := fd7h; " FIFO output part DRDY.clk = CLK; DRDY.aclr = !DREN; frph.clk = !READ; frph.aclr = wpclr; frph := frph + 1; DRDY := den & (pc & ^b1111 == ^b0010); Q = (frp == 0) & fd0w # (frp == 1) & fd1w # (frp == 2) & fd2w # (frp == 3) & fd3w # (frp == 4) & fd4w # (frp == 5) & fd5w # (frp == 6) & fd6w # (frp == 7) & fd7w; END