V53 and V53A (V53 below) are one of the NEC V series micrcontrollers. These are microcontroller that integrated some peripherals with V33 cored. Its peripherals are equivalent to V50's peripherals, so that V53 is a microcontroller that replaced V50's core-processor from V30 to V33.
And V33 core-processor has compatible instruction set as Intel 8086/80186 microprocessor.
| Core-Processor | V33 compatible |
| Sereial I/F | 1 channel (8251 compatible) |
| Timer/Counter | 3 channels (8254 compatible) |
| DMA | 4 channels (8237/8271 compatible) |
| Intrerupt Controller | 8 lines (8259 compatible) |
| BUS I/F | Address: 24bit (selectable address expantion capability like an EMS) Data: 8/16bit (Dynamic bus sizing) Address and Data bus are separated. Minimum two clocks/access. Programmable wait controller (0-7 wait) DRAM refresh controll. |
| Package | 132pin PGA. 120pin QFP. |
| Operating conditions | Operating Frequency: 2-20MHz Power consumption: 900mW (@16MHz) |
V33 is a super version of the V30 that separates address bus and data bus, executes all instrucitons with wired logic, not micro-codes. Therefore, V33 is two times faster than V30 at same clock frequency. V33 has the parformance equivalent to i80286.
It is difference on the core-processor V33 and V33A. At the V33, some intrurupt vector number such as undefined instruction fault are differnt to intel i80X86. At the V33A, these number are re-defined same as intel i80X86 prcessors.
Integrated peripherals of the V53 are mapped on I/O area, each peripherals can be located any address.
Each paripherals are independent of each other, therefore, requires extrenal wire when using them, especialy at the intrerupt controller.
V33 has a 16 bit based extrenal data bus, however, it can also changes bus width to fit connected devices. When external address decoder returens BS8 signal to V53, its BIU recoginize target device is 8 bit and accesses to target with only lower 8 bit data bus, this called Dynamic Bus Sizing. Therefore, there is not separate versions by bus size such as V20 and V30.
V53 has a programmable wait controler. It can set wait state for each area, I/O area, 6 blocks of memory area, refresh cycle, intrerupt acknowlidge cycle. Each areas can be programmed wait state from zero to seven, and also can be added from external.
When add any wait state from external, READY signal is sampled at the end of cycle. Therefore, there is not waste of time at adding wait state such as V25/V35.
When you require more informations, I recommend to refer to followings:
I tried to built a V53A board and edited report as actual use. Please refer to here.