In 1994, a high parformance 8 bit microcontroller was shipped from Kawasaki Steel Corp.(LSI division), and it became a subject of conversation. Well first released controller is the KL5C8012, it is cored with Z80 compatible processor, and integrated with 40 bits of PIO, a USART, three TIMER/COUNTER, a MMU and 512 byute of SRAM, packaged with 100pin QFP.
| Core Processor | KC82 (KC80+MMU) Z80 instruction compatible |
| Parallel Ports | 40 bits Some of them have alternative function |
| Serial Port | One channel (8251 compatible) |
| Timer/Counter | 5 channels |
| Intrerupt Controller | 16 levels (8 internal, 8 external) |
| Extrenal BUS Interface | Address: 19 bits Data: 8 bits |
| Internal RAM | 512 bytes |
| others | A clock generator, Debugging Interfase |
| Electrical Characteristics | Operating frequency: 0-10MHz Power consumption: 125mW (@5.0V,10MHz) |
| Package | 100pin QFP |
In addition to KL5C8012, some types are also available, integrated with DMAC, DRAM controller, HDLC interface or separated core processor.
Well, "Low power" and "High Speed" is one of the features of the KL5C80xx series. Surely these features are convincing.
High Speed: The KC80 core processor runs four times faster than Z80 at same clock frequency, so that the KC80 running at 10 MHz has same parformance as Z80-40MHz!!
Low Power: When KL5C8012 operating at maximum frequency, its power consumption is only 125mW (5V,25mA).
Number of execution clock cycles par instruction is depend to instruction byte length, most of clocks are spent to op-code feach and memory op-rands access. And at the final cycle of every instructions, next instruction code is fetched, so that one instruction is executed in one clock cycle minimum. Thus KC80 realizing to run four times faster than Z80 with reducing CPI.
But it is also weak point that to reduce CPI, when one wait state is added, parformance will slow down in half :-(
The KL5C8012 has two different modes to connect external memory, connecting memory device with extrenal address decoder (maximum mode) and connecting memory device directly (normal mode). At the normal mode, timing designing seems easy. But it is very difficult on the timing designing at higher operating frequency. Because the KL5C8012 running at minimum of one clock par instruction, so that the memory access cycle becomes executing in one clock cycle.
Actualy, running at 10 MHz with no wait state, the access time for the ROM is requires TACC < 44ns and TOE < 22ns include decoder delay. In normal mode, it can directly connects the memory IC, so that these timing value apply to the ROM. But fast ROM is difficult to get.
When insert one wait with the programable wait control unit, the timing values become TACC < 144ns and TOE < 122ns. But the KL5C8012 is very low CPI, One wait state makes slow down the operating speed in half.
Secondly, consider to slow down the clock frequency with no wait state. When operating clock frequency slow downs to 6.144MHz, reauired access timings become TACC < 75ns and TOE < 53ns. So normal ROM can be used.
The KL5C8012 has 512 bytes of intrenal RAM without wait state. So locate stack or any variables into the intrenal RAM and running at maximum clock frequency with one wait state may better way. This means to concern memory usage and programing technique, so that necessaly to make sure each case, that depends.
NOTE: KL5C80A16 and KL5C80A20 do not have internal SRAM.
Nowadays 15-20ns class fast SRAM for cache memory is appearing on the market. When use it and copy from ROM to SRAM at the start up, it can runs with no wait state at the high clock frequency. It can also use like a Shadow ROM without any extanal components with remap SRAM into ROM area with a MMU.
For the integrated wait controller, it can not particularly configures finely. Phyisical memory area is only separated in half, and there is some limits on configureing for each area. For the memory access, it can configures to 0 wait or 1+n wait. For the I/O access, it can configures to 1 wait or 2+n wait. "n" is added with RDY input. And KL5C8012 dose not has a DRAM reflesh controller, so connecting any DRAM is difficult.
NOTE: KL5C80A16 and KL5C80A20 has a DRAM controller, they can directly connect DRAMs.
KL5C8012 has internal pull-up resister for all I/O pins, so not used pins can be open state, and they will be fixed to "H" level.
NOTE: KL5C80A16 and KL5C80A20 do not have any internal pull-up.
For datails of the KL5C8012 and its families, please refer to the documents as follows.
I built a board computer with the KL5C8012, too. And edited as an example of actual use. Please refer to here.